Publicadas por Kalun Lau a la/s 1:24 a.m.
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Publicadas por Kalun Lau a la/s 7:23 p.m.
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Publicadas por Kalun Lau a la/s 12:03 p.m.
Saludos, a los que estan renovando o registrando una membresía al IEEE, les comunico que la Sociedad de Potencia y Energía (PES) y la Sociedad de Comunicaciones (COMSOC) poseen promoción de membresía gratuita a los que se registren al IEEE, para mayor información contactarse vía este medio.
Publicadas por Kalun Lau a la/s 12:25 a.m.
//Una gran historia de un emprendedor microelectronico.......
//Una de las partes mas interesantes:
Undeterred, Andreas started talking to EDA tool vendors and
semiconductor foundries. He quickly discovered that the entire suite
of EDA tools required for this sort of design can easily cost around
$1 million. Similarly, creating the photomasks for the design at his
targeted 65 nm technology node would also cost around $1 million. "The
end result was that if I did things the conventional way, this project
was going to cost much, much more than was in my bank account," says
Andreas, "so I decided NOT to do things the conventional way."
In the course of my travels around the world I have been fortunate enough to meet some truly great engineers. However, it's rare that I am completely blown away by someone on the engineering front. At least, this was true until I was introduced to Andreas Olofsson, president and architect of Adapteva Inc. (www.adapteva.com). As far as I am concerned, Andreas is "an engineer's engineer." This is a man who single-handedly invented a new computer architecture, designed his own System-on-Chip (SoC) from the ground up – including learning how to use all of the EDA tools – then took the device all the way to working silicon and a packaged prototype... and that's when things really started to get interesting!
How it all began
A few years ago, while working on various aspects of digital signal processing, Andreas began to ponder the problem that existing processing solutions – while very versatile – were not inherently efficient in terms of the number of floating-point operations (flops) that could be achieved per watt. Andreas was targeting really complex floating-point problems that require a massive amount of flops. This includes the obvious suspects such as radar, medical imaging, and communications infrastructure tasks like beam forming. But even battery-powered handheld applications increasingly require the ability to perform computationally-intensive tasks while consuming as little power as possible.
As Andreas told me, "It was obvious that the world needed extremely high-performance, low-power computational processing capabilities, but I felt that the existing market simply wasn't doing enough to satisfy these needs." Then Andreas had an epiphany – he realized that it would be possible to achieve his goal by creating an SoC comprised of a matrix of processing elements along with an associated on-chip network, all – as he says – "obsessively fine-tuned for miserly power consumption."
Andreas was well aware that this had been tried before – recent casualties in the market include Ambric with its Massively Parallel Processor Array (MPAA) architecture and structured object programming model, and MathStar with its Field-Programmable Object Arrays (FPOAs) and indescribable programming model. But he believed that, "(a) they came in too early and (b) they had problems with their programming models."
Andreas was a man with a vision. He believed in his heart and soul that he could solve the problem. Thus, on January 23, 2008, he left his existing job and – after a week's vacation with his wife to recharge his batteries – he felt ready to leap into action.
Defining and capturing the architecture
Upon returning from his vacation, Andreas formed his new one-man company, Adapteva, and then disappeared down into his basement. Week after week, he spent sixteen hours a day doing research, reading technical papers, and making notes. As he wryly comments: "I have a very understanding and supportive wife."
I had to question how Andreas was funding all of this effort, and he replied that he was using his pension money – basically, he was betting his entire future and that of his family on the belief that he could succeed on his own where much larger companies had failed. (Andreas is correct – he does have a very understanding and supportive wife!)
On the basis of his research, Andreas determined that the "best-of-the-best" existing solutions were achieving around 0.5 to 1.0 gigaflops per watt (Gfpw). Based on this, Andreas set his target as 50 Gfpw – that's real flops achievable in real-world applications (not marketing flops) – which would be 50 to 100X better than the competition.
Andreas started with his processor. Looking first at offerings from ARM and MIPS, he decided that there was no way he could use these processors to obtain the power-efficiency he required. "They're both great architectures," he notes, "they're just not good enough for what I had in mind – you can’t make something that will be everything to everybody."
So Andreas decided to design his own high-performance, low-power, ANSI-C programmable 32-bit floating-point processor from the ground up. The next step up was to design the rest of the node, which – in addition to the processor – contains 32 KB of local memory, a Direct Memory Access (DMA) engine, and a router. Andreas also designed the rest of the on-chip network, and a number of other elements such as high-speed input/output (I/O) SRAM buffer macros.
The entire architecture is fully scalable from 4 to 1,024 processing nodes. In the case of his first iteration, Andreas determined to create a chip containing a 4 x 4 = 16 matrix of processing nodes as illustrated in Figure 1. This decision was based on the fact that it's obviously simpler to create a 4 x 4 matrix than it would be to create a larger matrix. Also, having a smaller chip increases the market size; a larger chip would be of interest to a smaller market.
Publicadas por Ary a la/s 8:34 p.m.